1. Field of the Invention
This invention relates to a semiconductor memory cell and manufacturing method thereof, and particularly to a semiconductor memory cell in which capacitor electrodes are formed like a tunnel, with a bit line passing through the interior thereof so that distortion of patterning is decreased while capacitance of the capacitor is increased.
2. Description of the Prior Art
A structure of a stacked capacitor cell (or "STC") and its manufacturing method are known in the art. Such a conventional cell has been described as a shielded bit line, and is formed with storage capacitors on bit lines. This type of conventional memory cell and manufacturing method and its layout, illustrated in FIG. 1, are considered a technique with some similarity to the present invention. One of these conventional STC cells is disclosed in U.S. Pat. No. 4,970,564, issued on Nov. 13, 1990 to Kimura et al.
FIG. 1(E) illustrates a small part of the layout of such a conventional STC cell. Active region 10, where elements are to be formed, is tilted at an angle of 45.degree. with respect to the word line and the bit line that meet at a right angle with each other, enabling storage electrode 18 to be arranged very densely.
FIGS. 1(A) to (D) are cross sectional views taken along line 1A--1A of FIG. 1(E) that illustrate the steps of fabricating such a conventional STC cell.
Referring to FIG. 1(A), field and active regions are partitioned on semiconductor substrate 11, and then source and drain regions 12 and gate electrode 13 are formed. Gate electrode insulating oxide film 14 is deposited and a bit line contact is opened by a photolithographic process. Thereafter, as illustrated in FIG. 1(B), a refractory metal or polysilicon layer (used to form a bit line) and oxide film 16 are deposited, and then bit line 15 is formed by patterning the deposited layers by utilizing a photoresist film as a mask. Thereafter, the photoresist film is removed, resulting in the structure of FIG. 1(B) .
Successively, as illustrated in FIG. 1(C), an oxide film is deposited and etched back without the photoresist film mask, and oxide side wall 17 is formed on bit line side walls, and a buried contact connecting the active region and a storage electrode are formed. As illustrated in FIG. 1(D), storage electrode 18, capacitor dielectric film 19 (an electrical insulator) and plate electrode 20 are formed in turn, and thereby a memory cell is produced.
The conventional memory cell manufactured by the method as described above, as illustrated in FIG. 1(E), is arranged such that bit line 15 and word line 13 intersect orthogonally with each other, and active region 10 is angled relative to bit line 15 and word line 13.
However, since bit line 15 is formed before the capacitor, a contact in the active region between the drain and the storage node (electrode) of the capacitor should be formed at a location over which the bit line does not pass. Accordingly, the active region should be disposed so as to be in a diagonal direction relative to the bit line and word line. Therefore, since the active region of the cell includes a tilted portion making an angle of 45.degree. with respect to word line 13 and bit line 15, distortion occurs in the photolithographic process for patterning the active region. Thus, a difficulty exists with this process, and unit cell area is not decreased.